Foundry mapping is a process of mapping an IC (integrated circuit) design onto a fabrication process used in a foundry. Different foundries conventionally have different fabrication processes and design rules. Being able to readily map an IC definition onto different fabrication processes is a long sought-after goal in the IC industry. However, this goal tended to be very difficult in standard cell architecture because the emphasis has been on extracting the maximum possible performance out of any particular process. For example, the actual libraries that define the cell characteristics are often pressing the corner cases of the process, and only when a device specified does not work (because timing is not met or because there is leakage or for some other reasons) does the IC designer adjust the process/design until the IC designer squeezes the IC design into the product parameters that are operable. Because the problem of readily mapping an IC definition onto different fabrication processes was insufficiently constrained (too many variables) in standard cell architecture, the problem proved to be intractable computationally.
MOSIS (Metal-Oxide Semiconductor Implementation Service) takes a very high-level abstract specification of an IC, circuit characteristics and parameters, and maps the IC onto any of several existing processes. For example, MOSIS may map an IC to any of a number of foundry processes. Indeed, MOSIS may even allow an IC to be mapped to foundry processes of different generations including a 0.25 micrometer process, a 0.18 micrometer process, a 0.13 micrometer process, and the like.
The reason that MOSIS renders the problem of readily mapping an IC definition onto different fabrication processes computationally tractable is that MOSIS detunes the performance and density characteristics of the mapping. However, the extent of the detuning is such that MOSIS does not produce the degree of performance optimality or packing density optimality required in a commercial design. In other words, MOSIS mapping is mostly used for academic proof-of-concept, not for commercially viable products.
Thus, it would be desirable to provide a method and apparatus for readily mapping commercially viable IC design (e.g., platform-based design) to multiple foundry processes.